Sr Principal Design Engineer
Core
Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms.
Role type
Senior Principal Design Engineer (Memory IP & Verification)
Builds
System-level memory IP models for hardware verification products
Domain
Semiconductor / Hardware Verification / Memory Subsystems
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog RTL design, RTL verification methodologies, complex protocol debugging, system-level architecture, project planning, technical documentation
Preferred skills
Cadence simulation/emulation products, hardware emulation platforms, Perl/Tcl/C-shell scripting, memory subsystem architecture, reusable IP model development
Technologies
Verilog, SystemVerilog, LPDDR, HBM, NAND Flash, eMMC, SD Card, DFI, UFS, Cadence tools
Responsibilities
Design and develop memory IP models for various interfaces; maintain and enhance existing products; execute verification strategies; diagnose and resolve complex RTL and system issues; create technical documentation; collaborate with cross-functional teams; manage project schedules and priorities.
Seniority
Senior, hands-on IC
