Sr Principal Design Engineer
Core
Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms.
Role type
Senior Principal Design Engineer (Memory IP & Verification)
Builds
System-level memory IP models for hardware verification products
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models
Required skills
Verilog/SystemVerilog RTL design, RTL verification methodologies, complex protocol debugging, memory subsystem architecture, project planning, technical documentation
Preferred skills
Cadence simulation/emulation products, hardware emulation platforms, Perl/Tcl/Tk scripting, reusable IP model development
Technologies
Verilog, SystemVerilog, LPDDR, HBM, NAND Flash, eMMC, SD Card, DFI, UFS, Cadence tools
Responsibilities
Design and develop memory IP models; Maintain and enhance existing products; Execute verification strategies; Diagnose and resolve complex RTL/protocol issues; Create technical documentation; Collaborate with cross-functional teams; Manage project schedules and priorities
Seniority
Senior, hands-on IC
