Senior / Staff Engineer - Digital Design
Core
Perform RTL-to-gate synthesis and Static Timing Analysis (STA) to generate optimized gate-level netlists and ensure timing closure for hardware designs.
Role type
Senior IC digital design engineer (physical design)
Builds
Optimized gate-level netlists and timing-closed hardware designs
Domain
Semiconductor / Hardware Engineering
Required skills
RTL-to-gate synthesis, Static Timing Analysis (STA), timing closure, ECOs, crosstalk and noise analysis, physical design optimization, scripting (Python, Tcl, Perl)
Preferred skills
Floorplanning, placement, routing, cell sizing
Technologies
Synopsys Design Compiler, Synopsys Fusion Compiler, Cadence Genus, Synopsys PrimeTime, Cadence Tempus, ICC2, Innovus
Responsibilities
Perform RTL-to-gate synthesis using EDA tools to generate optimized gate-level netlists; Run Static Timing Analysis (STA) including setup/hold checks across pre- and post-layout stages; Collaborate with design, verification, and PD teams to ensure timing closure and design optimization; Assist in the development and maintenance of synthesis and STA scripts and methodologies; Analyze and resolve timing issues; Run timing constraint checks and logic equivalency checks (LEC); Participate in design reviews and provide feedback on timing and synthesis aspects; Document and report synthesis and STA results, highlighting key findings and recommendations.
