Frontend Design / Timing Constraints Lead
Core
Lead the development and verification of timing constraints for digital IP and System-on-Chip (SoC) designs to ensure timing closure and performance targets.
Role type
Senior IC SoC Timing Constraints Lead
Builds
Digital IP and SoC designs meeting timing, power, and area targets
Domain
Semiconductor / Digital SoC Design
Required skills
SoC timing constraints, Static Timing Analysis (STA), digital circuit design, SoC IO protocols, constraint verification, EDA tools, timing closure, power optimization, area optimization
Preferred skills
Agentic AI for constraints development, synthesis, place & route collaboration, silicon bring-up
Technologies
EDA tools, STA tools, SoC design flows
Responsibilities
Define and apply timing constraints to meet performance and power targets; perform Static Timing Analysis (STA) and debug timing violations; collaborate with synthesis, place & route, and verification teams to achieve design closure; participate in design reviews and contribute to technical documentation; support integration and bring-up of digital blocks on silicon.
Seniority
Senior, hands-on IC
