Silicon Front End CAD Verification Engineer
Core
Architect scalable DV environments and develop high-quality VIP for ASIC/FPGA verification using SystemVerilog/UVM, integrating AI tools for testbench creation and regression triage.
Role type
Senior IC silicon front-end CAD verification engineer (methodology & AI)
Builds
Reusable testbench architectures, qualified DV flows, and AI-driven automation for Ericsson's 5G/6G ASIC and FPGA programs.
Domain
Semiconductor verification (ASIC/FPGA) and Telecommunications infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, SVA, formal verification, Python scripting, Jenkins CI/CD, EDA tool expertise (Cadence Xcelium/Synopsys VCS), AI/LLM tool integration
Preferred skills
Register-model development (UVM RAL, SystemRDL), IP-XACT, migrating verification environments between EDA vendors
Technologies
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Jenkins, OneRun, ChipAgents, Kiro
Responsibilities
Architect scalable DV environments with automated regression; Develop efficient, reusable UVM verification IP; Advance verification methodology across IP-to-SoC flows; Apply AI tools for testbench creation and regression triage; Automate regression and release qualification in CI/CD pipelines; Mentor engineers and resolve complex flow/tool issues
Seniority
Senior, hands-on IC
