Design Verification Engineer
Core
Verify functional correctness and robust design for custom AI-native silicon and system-level solutions powering frontier AI models.
Role type
Senior Design Verification Engineer (SoC/IP)
Builds
AI-native silicon chips, subsystems, and full SoC-level functionality for OpenAI's supercomputing platform.
Domain
Semiconductor hardware design, AI accelerators, computer architecture
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random verification, directed testing, bug triage, root cause analysis, regression infrastructure, coverage analysis
Preferred skills
formal verification, emulation, performance modeling, memory/cache systems, coherency, interconnects, ML compute primitives
Technologies
SystemVerilog, UVM, VCS, Questa, Verdi
Responsibilities
Own verification of custom IP blocks, subsystems, or full-chip SoC; define verification plans based on architecture specs; develop testbenches; build stimulus generators, checkers, monitors, and scoreboards; drive bug triage and resolution; contribute to regression infrastructure and coverage closure
Seniority
Senior, hands-on IC
