Physical Design Engineer, ML4PD
Core
Physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout.
Role type
mid- to senior-level Physical Design Engineer (ASIC)
Builds
end-to-end ASICs for AI/ML platforms
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
logic design fundamentals, synthesis, place-and-route flows, physical design tools, timing closure, power optimization, floorplanning, clocking, I/O planning, area improvement, Tcl, Perl, Shell, Python, low-power techniques (power gating, multi-Vt, voltage scaling)
Preferred skills
experience with EM/IR analysis, familiarity with advanced AI/ML silicon development
Technologies
synthesis tools, place-and-route tools, physical design tools
Responsibilities
optimize floorplanning, timing, power, performance, and area across multiple IPs; contribute to clocking, I/O planning, timing closure, area improvement, and power optimization; collaborate with front-end and physical design engineers
Seniority
mid- to senior-level, hands-on IC