Mixed Signal IC Layout Engineer
Core
Full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts for high-performance SoCs.
Role type
Senior IC Layout Engineer (Mixed Signal)
Builds
High-speed analog/mixed-signal blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os) integrated into D2D PHYs
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Required skills
Full-custom layout, Synopsys Custom Compiler, Cadence Virtuoso, Synopsys ICV, Siemens Calibre, CMOS/FinFET nodes, EM/IR analysis, ESD design, Latch-up prevention, DRC/LVS/ERC/DFM closure
Preferred skills
Python, Tcl, SKILL scripting for automation
Technologies
TSMC, Samsung, FinFET, 12nm–2nm nodes
Responsibilities
Execute full-custom layout for key blocks from schematics to GDSII; Develop optimized floorplans, placement, and routing; Apply best practices to optimize parasitics, coupling, IR drop, and electromigration; Support post-layout extraction and simulation
Seniority
Senior, hands-on IC
