ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Core
Design and optimize high-performance, power-efficient custom SoCs (System on Chip) for AWS Machine Learning inference servers, specifically the Inferentia architecture.
Role type
Senior IC ASIC Design Engineer
Builds
Custom ML inference datacenter servers (Inferentia)
Domain
Cloud computing, Machine Learning hardware acceleration, SoC design
Deliverable
production ML models | product features
Required skills
ASIC design, SystemVerilog RTL development, microarchitecture design, synthesis and timing closure, lint and clock domain crossing checks, debugging architecture and algorithms, multi-level logic verification (IP blocks to SoC)
Preferred skills
Formal verification techniques, ARM and DSP ISAs experience, RF standards (4G/5G NR, WiMAX, 802.11ad), Python or Perl scripting for automation
Technologies
SystemVerilog, Python, Perl, ARM, DSP ISAs
Responsibilities
Develop high-performance RTL designs meeting project targets; analyze microarchitectures to optimize power, performance, and area; create microarchitectures and deliver timing-clean designs; execute quality checks for design integrity; collaborate with architects, verification, and back-end teams.
Seniority
Senior, hands-on IC
