Principal Advanced Packaging Engineer
Core
Lead R&D for next-generation packaging technologies for optical chips (NPO and CPO products), setting technical direction and driving development of 2.1D, 2.5D, and 3D integration.
Role type
Principal Advanced Packaging Engineer (senior IC)
Builds
Next-generation optical chip packaging solutions (NPO and CPO)
Domain
Semiconductor manufacturing / Optical interconnects
Deliverable
production ML models | product features | research | infrastructure
Required skills
Advanced packaging processes (2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, overmold), Silicon photonics chip packaging, EIC-to-PIC integration, Packaging material selection and qualification, OSAT and tool vendor partnership, PDK development and design rule authoring, Yield analysis and reliability characterization (Cpk, SPC)
Preferred skills
CPO or NPO product development, Optical coupling and waveguide alignment, DFM and DFT for advanced packaging
Technologies
CXL, Ethernet, NVLink, PCIe, UALink, COSMOS
Responsibilities
Lead R&D for advanced packaging of optical chips; Define and optimize wafer-level, panel-level, or die-level packaging process flows; Drive EIC-to-PIC integration; Select and qualify packaging materials; Partner with OSAT, tool vendors, and material suppliers; Characterize and improve yield, reliability, and process capability; Develop and maintain packaging PDKs and design rules
Seniority
Principal, hands-on IC with technical leadership