Tech Lead, STA
Core
Own top-level timing closure and signoff for next-generation connectivity silicon powering rack-scale AI infrastructure.
Role type
Principal Engineer, Static Timing Analysis (STA)
Builds
PCIe, CXL, UALink, and Ethernet platforms for hyperscalers
Domain
Semiconductor hardware design, AI connectivity infrastructure
Deliverable
production ML models
Required skills
Full-chip STA signoff, advanced process node timing (5nm/4nm/3nm), PrimeTime/PrimeTime SI expertise, SDC constraint development, clocking architecture analysis, CDC resolution, Tcl/Python/Perl scripting for automation
Preferred skills
High-speed connectivity SoC experience (PCIe Gen 6/7, CXL, UALink), hierarchical STA, ETM/ILM models, low-power signoff (UPF/CPF), multi-voltage domain timing
Technologies
PrimeTime, PrimeTime SI, Tcl, Python, Perl, SDC, UPF, CPF, PCIe, CXL, UALink, Ethernet
Responsibilities
Drive timing convergence from floorplan to tapeout on advanced nodes, define and evolve STA methodology and signoff criteria, partner with Physical Design, RTL, DFT, and CAD teams, mentor STA engineers, influence EDA vendor engagements and STA roadmap
Seniority
Principal, hands-on IC with strategic influence
