Tech Lead, Formal Verification
Core
Lead formal verification efforts for complex IP and SoC designs to ensure first-pass silicon success for next-generation connectivity and AI infrastructure products.
Role type
Tech Lead, Formal Verification Engineer
Builds
Custom connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
formal verification, assertion-based verification, property checking, SystemVerilog, SVA, Python scripting, root-cause analysis, technical leadership
Preferred skills
JasperGold, VC Formal, high-speed protocol verification, NoC architectures, cache coherency protocols, simulation, emulation
Technologies
JG, VCF, SystemVerilog, Python, Perl, Tcl, Shell, CXL, Ethernet, NVLink, PCIe, UALink
Responsibilities
Develop comprehensive formal verification plans from architecture and design specifications; Develop and execute formal verification environments, assertions, properties, and checkers; Drive proof convergence through advanced abstraction and complexity reduction techniques; Collaborate with RTL designers, architects, and verification teams to understand design intent; Evaluate, deploy, and scale formal verification methodologies, flows, and tools across projects; Improve verification productivity through reusable methodologies, automation, and best practices; Ensure comprehensive design correctness and provide technical leadership and mentorship; Drive bug triage, root-cause analysis, and resolution; Support project planning by estimating verification effort, tracking execution progress, and driving mitigation plans; Participate in design reviews and contribute to verification sign-off strategies; Promote assertion-driven design practices across engineering teams
Seniority
Senior, hands-on IC with leadership responsibilities
