<Data center>Senior Signal and Power Integrity Engineer
Core
Lead technical efforts in Power Integrity (PI) and Signal Integrity (SI) signoff, modeling, and optimization for high-speed IO interfaces and power delivery networks across package, PCB, die, interposer, and substrate designs.
Role type
Senior IC PISI Technical Leader
Builds
High-speed IO interface systems and power delivery networks for semiconductor packages and boards
Domain
Semiconductor hardware design / High-speed electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Power Integrity analysis, Signal Integrity analysis, high-speed IO interface simulation, PDN analysis, system-level simulation, commercial SI/PI tooling, package design optimization, PCB design optimization, die/interposer/substrate modeling
Preferred skills
Customer-facing technical leadership, cross-functional collaboration
Technologies
PCIe, SerDes, commercial SI/PI simulation tools
Responsibilities
Guide customers to complete Signal Integrity and Power Integrity signoff, Model and optimize vias, connectors, sockets, breakouts, and various system components, Perform system-level signal integrity simulation in high-speed IOs, Architect and simulate power delivery systems including multiple dies and substrates, Collaborate with multiple teams to optimize package, PCB, die, interposer, and substrate designs
Seniority
Senior, hands-on IC
