Manager, Package Design Engineering
Core
Lead and scale the Package Design team to deliver end-to-end IC packaging solutions (FCBGA/FCCSP, monolithic, multi-die, chiplet) for advanced AI infrastructure and connectivity products.
Role type
Manager, Package Design Engineering
Builds
Advanced IC packaging solutions enabling PCIe, CXL, and Ethernet connectivity for hyperscale AI customers
Domain
Semiconductor / Advanced Packaging / AI Infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
End-to-end package design (FCBGA/FCCSP, monolithic, multi-die, chiplet), Substrate stack-up and routing strategy, High-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G+), OSAT and substrate vendor collaboration, Design for manufacturability (DFM) and yield optimization, Cross-functional chip-package-board co-design, Design methodology and automation development
Preferred skills
Master's degree in EE, Automation scripting (Python, SKILL, Tcl), Early package feasibility and platform evaluation, Chip floor planning and system-level tradeoffs, SIPI modeling and thermal/mechanical performance analysis
Technologies
Cadence Allegro APD/SiP, 7nm/5nm/3nm nodes, 2.5D/3D integration, CPO/CPC, Heterogeneous integration
Responsibilities
Build and mentor a high-performing package design engineering team, Own end-to-end package design execution from concept feasibility through tape-out and production ramp, Define design templates, standards, and best-known methods (BKMs), Lead design reviews, audits, and issue resolution, Partner with SIPI, silicon architecture, and system/board design teams, Collaborate with OSATs and substrate vendors to ensure design feasibility and alignment with technology roadmaps
Seniority
Manager, hands-on IC leadership
