Advanced Packaging & Power Delivery Senior Engineer
Core
Designing power-delivery architecture and advanced packaging for next-generation AI accelerators, spanning on-die grids to multi-chiplet 3D-integrated systems.
Role type
Senior IC analog/power delivery and packaging engineer
Builds
High-performance AI accelerator chips and multi-chiplet 3D-integrated systems
Domain
Semiconductor hardware design, AI accelerators, advanced packaging
Deliverable
production ML models
Required skills
on-die power grid design, package/PCB PDN analysis, 2.5D/3D IC packaging, multi-chiplet integration, interposer/substrate co-design, SI/PI verification, EDA tool proficiency
Preferred skills
thermal modeling, co-simulation, AI accelerator custom ASIC flows, OSAT/vendor collaboration
Technologies
EDA tools for power integrity and PDN simulation
Responsibilities
Own end-to-end power-delivery design from on-die to PCB; Lead advanced packaging architecture for 2.5D/3D stacking; Perform SI/PI verification and sign-off; Collaborate with Silicon Engineering to align solutions; Support thermal and integration reviews; Develop power-delivery methodology and guidelines; Mentor team members; Engage with external substrate/OSAT partners
Seniority
Senior, hands-on IC
