Senior/ Staff Package Design Engineer
Core
Design and qualify advanced IC packaging solutions for high-performance connectivity silicon to enable AI scale-up and scale-out systems.
Role type
Senior IC Package Design Engineer
Builds
Custom connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies
Domain
Semiconductor hardware / AI infrastructure / High-speed connectivity
Deliverable
production ML models | product features
Required skills
IC package design, organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS 2.5D/3D integration, signal integrity (SI), power integrity (PI), thermal management, package layout, substrate routing, bump/ball maps, stack-ups, materials selection, DFM, OSAT engagement
Preferred skills
AI interface experience, PCIe/CXL, package reliability standards (JEDEC/IPC), chiplet-based architectures, heterogeneous integration
Technologies
Cadence APD / SiP, BGA, FCBGA, FCCSP, CoWoS
Responsibilities
Execute end-to-end IC package design from feasibility to high-volume manufacturing; Implement package architecture using advanced technologies; Drive SI, PI, and thermal considerations; Perform package layout and materials selection; Collaborate with silicon, SerDes, and system teams; Interface with OSATs and manufacturing partners; Conduct risk assessments and failure analysis
Seniority
Senior, hands-on IC
