MTS - Analog Layout
Core
Lead full-custom layout for complex Analog/Mixed-Signal IP blocks (Bandgap, LDOs, PLLs, etc.) from floor-planning to tape-out, ensuring yield, reliability, and DFM compliance in advanced nodes.
Role type
Senior IC Analog Layout Engineer (AMS)
Builds
High-performance Analog/Mixed-Signal IP blocks for memory and storage solutions
Domain
Semiconductor / Analog IC Design
Required skills
Full-custom analog layout, Advanced FinFET node expertise (3nm, 5nm), Planar CMOS knowledge (40nm+), DRC/LVS/ERC signoff, Python scripting, EDA automation, AI/ML concepts for layout optimization
Preferred skills
Mentorship of junior engineers, IP reuse strategy, AI-driven methodology development
Technologies
Python, EDA tools, TSMC PDKs, Advanced metal stacks
Responsibilities
Lead layout for complex AMS blocks, Own layout quality from floor-planning to tape-out, Drive DRC/LVS/ERC/ANTENNA checks, Provide technical guidance and design reviews, Establish best-known methods (BKMs), Develop AI-assisted layout solutions
Seniority
Senior, hands-on IC with mentorship responsibilities
