ASIC Analog Layout Engineer
Core
Physical implementation of high-speed analog and mixed-signal circuits for ASICs used in Micron's tester and controller IP.
Role type
Senior IC analog layout engineer
Builds
Custom analog and mixed-signal layouts for high-speed ASIC applications
Domain
Semiconductor / Analog IC Design
Required skills
Custom analog and mixed-signal layout, Physical verification (DRC, LVS, ERC), Semiconductor process technologies, Parasitic analysis and extraction, Automation scripting (SKILL, Python, PVL)
Preferred skills
Advanced process technologies (FinFET 16nm or below), High-speed circuit blocks (SerDes, PLL, DLL, PHY), Parasitic extraction tools (Quantus Insight, ParagonX), AI-enabled workflow tools
Technologies
Cadence Virtuoso, Quantus Insight, ParagonX, SKILL, Python, PVL
Responsibilities
Develop high-quality custom analog and mixed-signal layouts, Perform physical verification checks, Optimize layouts for signal integrity and reliability, Develop automation and scripting solutions, Troubleshoot layout environment and tool issues
Seniority
Mid-to-Senior, hands-on IC
