ASIC Design Engineer, DMTS/SMTS/MTS
Core
Design and CAD enablement for advanced semiconductor products (NAND, DRAM, HBM, SoC, mixed-signal), focusing on automation, physical design, timing signoff, and custom layout.
Role type
Senior IC ASIC Design Engineer (CAD/Physical Design)
Builds
Scalable CAD tools, automation frameworks, design flows, and methodologies for memory and storage products.
Domain
Semiconductor / VLSI / Memory and Storage
Required skills
VLSI and CMOS fundamentals, EDA environments (Cadence, Synopsys, Siemens), Unix/Linux, scripting (Python, Tcl, SKILL, Shell, Perl, C/C++, Java, Lisp), physical design (floor planning, placement, CTS, routing), timing signoff (STA, multi-corner/multi-mode), DFT (scan, ATPG, MBIST, LBIST), analog/custom layout, parasitic extraction, simulation, DRC/LVS.
Preferred skills
AI-assisted engineering solutions, AI coding techniques, mentorship, cross-functional leadership.
Technologies
Cadence Innovus, Virtuoso, Synopsys ICC2, PrimeTime, Siemens Tessent, Cadence Tempus, Modus
Responsibilities
Develop and maintain infrastructure for circuit build capture, layout, simulation, characterization, implementation, physical verification, and signoff workflows; Lead implementation and signoff activities across physical design, static timing analysis, and design for test; Drive floor planning, power planning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification; Perform parasitic extraction and modeling, and support circuit simulation, design validation, reticle experiments, tape-out revisions, and post-layout correlation; Partner with architecture, RTL, circuit design, verification, and process technology teams to ensure design readiness and manufacturability.
Seniority
Senior, hands-on IC
