Lead Layout Engineer
Core
Develops block, macro, or chip level layouts and floorplans for Power Management (PMIC) modules, creating area and parasitic efficient designs that meet project specifications.
Role type
Senior IC layout engineer (analog/PMIC)
Builds
Custom analog layouts for Linear and Switching Regulators, ADCs, DACs, CHARGERS, Envelope Trackers, APTs, High Current POWERFETS, OTAs, Error Amplifiers
Domain
Semiconductor / Analog IC Design
Required skills
Floor planning, Signal planning, Analog layout fundamentals, Physical verification debugging, Submicron/Deep-submicron/High Voltage CMOS process knowledge, Parasitic extraction, Scripting (SKILL/PERL/SHELL)
Preferred skills
SOI process knowledge, AI based layout development flow, Scripting (SKILL/PERL/SHELL)
Technologies
Cadence Virtuoso IC201+, Calibre Verification Suite, LVS, rmap
Responsibilities
Develop block, macro, or chip level layouts and floorplans; Conduct analyses, tests, and verify designs using different tools and techniques; Create area and parasitic efficient layouts; Perform physical verification debugging using Calibre Verification Suite.
Seniority
Senior, hands-on IC
