PMIC Design Verification Lead (Sr Staff Engineer)
Core
Leading digital verification for next-gen PMIC technologies, Mixed-Signal IPs, ASICs, and Chipsets used in Qualcomm Snapdragon power solutions.
Role type
Senior Staff IC Digital Verification Engineer (PMIC/Power Management)
Builds
High-performance, high-quality, low-power world-class products including 5G/6G power solutions and 100W+ charging technologies.
Domain
Semiconductors / Power Management ICs (PMIC) / ASIC Design
Required skills
ASIC design and verification, UVM (Universal Verification Methodology), System Verilog, Test planning and architecture, Coverage closure, Debugging complex systems (SOCs, firmware, embedded sequencers), Mixed-signal IP verification
Preferred skills
Analog behavioral models, Team leadership, Python or Perl scripting, Expert-level System Verilog, Writing independent test plans
Technologies
System Verilog, UVM, Python, Perl, SOC, Firmware, Embedded sequencers, ADCs, DC-DC charge pumps, Buck regulators, Linear regulators
Responsibilities
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development; Lead digital verification from test planning to coverage closure; Partner with international teams from system definition to high-volume OEM launches; Debug complex systems including SOCs and firmware; Mitigate project risks and plan tasks.
Seniority
Senior Staff, hands-on IC with leadership responsibilities
