SoC STA/Timing Engineer (Senior Staff/Principal)
Core
Perform Static Timing Analysis (STA) setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain System-on-Chip (SoC) and SubSystem designs.
Role type
Senior Staff/Principal SoC STA/Timing Engineer
Builds
High-performance SoCs and SubSystems for mobile and connected devices
Domain
Semiconductor hardware design, ASIC back-end flows
Required skills
STA fundamentals, AOCV/POCV concepts, CTS, timing constraints, PrimeTime, Tempus, ICC2, Innovus, signal integrity, cross-talk noise, parasitic extraction, TCL, Perl, Python, Spice simulations (Hspice, FineSim)
Preferred skills
Chip-level and hard-macro level timing convergence, RTL-to-GDSII flows
Technologies
PrimeTime, Tempus, ICC2, Innovus, Hspice, FineSim, TCL, Perl, Python
Responsibilities
Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs; Validate and debug timing across multiple PVT conditions; Run STA flows and correlate Spice to STA results; Evaluate timing methodologies/tools and automate STA/PD flows; Handle timing ECOs and logical equivalence checks; Mentor junior engineers in timing flows and methodologies
Seniority
Senior Staff/Principal, hands-on IC with mentorship
