Staff Engineer – STA Methodology/CAD
Core
Drive development, deployment, and enhancement of next-generation Static Timing Analysis (STA) methodologies for complex SoCs.
Role type
Staff IC STA Methodology/CAD Engineer
Builds
Timing signoff flows, automation infrastructure, and timing closure solutions for advanced technology nodes.
Domain
Semiconductor hardware engineering (VLSI/SoC design)
Required skills
Static Timing Analysis (STA), MMMC timing signoff, timing constraints (SDC), setup/hold closure methodologies, SOCV/AOCV derates, ECO and timing convergence techniques, Tcl scripting, Python scripting, EDA tool expertise (Synopsys PrimeTime, Cadence Tempus)
Preferred skills
Advanced technology nodes (7nm and below), timing automation frameworks, Synthesis/Physical Design/DFT knowledge, AI/ML-driven timing optimization
Technologies
Synopsys PrimeTime, Cadence Tempus, Tcl, Python, Perl
Responsibilities
Define and improve STA methodologies for block, subsystem, and full-chip designs; Drive timing signoff flows including MMMC analysis and constraint validation; Develop automation and infrastructure to improve timing analysis efficiency; Debug complex timing issues and provide scalable solutions; Mentor junior engineers and provide technical leadership.
Seniority
Senior, hands-on IC with technical leadership
