Physical Design Engineer, Senior Lead
Core
Senior Lead Physical Design Engineer responsible for ASIC design flow from netlist to GDS2, including floorplanning, placement and routing, clock tree synthesis, and sign-off closure.
Role type
Senior Lead IC Physical Design Engineer
Builds
ASIC chips for mobile and connected devices
Domain
Semiconductor / Hardware Engineering
Required skills
ASIC Place and Route flow, Netlist to GDS2 ownership, Voltage Islands, Low power methodologies, Congestion and CTS debugging, PnR tools (Innovus/Fusion compiler), Sign-off methodology (PV/PDN/STA/FV/CLP/Scan-DRC), Scripting (TCL/PERL/PYTHON)
Preferred skills
Global team collaboration, Methodology improvement
Technologies
Innovus, Fusion compiler, TCL, PERL, PYTHON
Responsibilities
Execute complete PD ownership from netlist to GDS2, Implement low-power methodologies, Debug congestion and CTS issues, Perform sign-off checks (PV/PDN/STA/FV/CLP/Scan-DRC), Improve existing design flows
Seniority
Senior, hands-on IC
