NPU AI/Processor Synthesis Engineer- Sr Lead
Core
Drive RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators (NPUs) used in next-generation SoCs.
Role type
Senior IC NPU AI/Processor Synthesis Engineer
Builds
High-performance AI/ML accelerator IPs and subsystems for SoCs
Domain
Semiconductor hardware design (ASIC) for AI/ML
Deliverable
production ML models
Required skills
RTL synthesis, timing closure, constraint development, Synopsys Design Compiler/Fusion Compiler, Cadence Genus, PrimeTime, low-power design (UPF), TCL/Python/Perl scripting
Preferred skills
AI/ML accelerator architecture, advanced technology nodes (5nm/4nm/3nm), physical-aware synthesis, hierarchical design, tapeout experience
Technologies
Synopsys Design Compiler, Fusion Compiler, Cadence Genus, PrimeTime, UPF, TCL, Python, Perl
Responsibilities
Own RTL-to-gate synthesis and timing closure; Develop and maintain synthesis flows and automation; Drive pre-layout and post-layout timing closure; Optimize designs for PPA targets; Create and validate timing constraints (SDC); Collaborate with cross-functional teams to resolve convergence issues; Perform quality checks (LEC, CDC, lint); Analyze and improve synthesis QoR via scripting; Support tapeout activities.
Seniority
Senior, hands-on IC
