Senior SoC Power Analysis & Optimization Engineer
Core
Develop and maintain power estimation methodologies, energy models, and perform RTL/gate-level power analysis for AI accelerator SoCs to optimize compute, memory, and interconnect subsystems for AGI workloads.
Role type
Senior IC SoC Power Analysis & Optimization Engineer
Builds
High-performance, sustainable silicon for AI accelerators and GenAI systems
Domain
Semiconductor / AI Hardware / SoC Design
Deliverable
production ML models | product features
Required skills
SoC design, computer architecture, ASIC low-power design, RTL/gate-level power analysis, Python/Perl scripting, power estimation methodologies
Preferred skills
Verilog/SystemVerilog, clock distribution/gating, synthesis/STA/place-and-route, power analysis tools (Joules, PowerArtist, PrimeTime PX), power management techniques (power gating, dynamic power management), pre-silicon vs silicon correlation, AI workload characterization
Technologies
Joules, PowerArtist, PrimeTime PX, Verilog, SystemVerilog, Python, Perl
Responsibilities
Develop power estimation methodologies and energy models; Perform RTL, gate-level, and post-layout power analysis; Analyze AI workloads to identify power reduction opportunities; Drive power optimization across compute, memory, and interconnect subsystems; Collaborate with architects and RTL designers on power-efficient microarchitecture; Work with physical design teams on implementation trade-offs; Develop automation scripts and dashboards for power analysis
Seniority
Senior, hands-on IC
