Physical Design Engineer
Core
Develop tools, flows, and methodologies for physical implementation of datapath and interconnect solutions for next-generation AI accelerators.
Role type
Senior IC physical design engineer (AI silicon)
Builds
Power, performance, and area (PPA) optimized silicon blocks for AI-native chips
Domain
Semiconductor hardware design / AI accelerators
Deliverable
production ML models | product features
Required skills
physical design and methodology, block physical implementation, PPA convergence, Python, Bazel, TCL, microarchitecture, RTL design, circuit design, physical verification, timing closure, EDA tools (physical synthesis, PNR, LEC, power estimation)
Preferred skills
AI or HPC chip experience, high-performance compute core optimization, top-level design methodologies
Responsibilities
Develop and own tools/flows/methodologies for physical implementation; Own physical implementation of floorplan blocks from floorplanning to final signoff; Collaborate with RTL designers for optimal block implementation; Analyze and optimize design for timing, power, and area trade-offs
Seniority
Mid-level IC engineer (2+ years experience)