SoC STA Engineer
Core
Static Timing Analysis (STA) setup, convergence, and signoff for multi-mode, multi-voltage domain designs in SoC development.
Role type
Senior IC Static Timing Analysis Engineer
Builds
SoC chips and digital/analog/RF systems
Domain
Semiconductor / VLSI / Hardware Engineering
Required skills
Static Timing Analysis (STA), PrimeTime/Tempus, timing analysis and validation, PVT conditions, timing constraints, AOCV/POCV, CTS, Latch transparency, multi-cycle path handling, TCL/Perl/Python scripting, RTL to GDS flow, Spice simulation, Signal Integrity, Layout Parasitic Extraction
Preferred skills
Chip-level and Hard-Macro timing convergence, cross-talk noise analysis, ASIC back-end design flows (ICC2, Innovus), device physics, Awk scripting
Technologies
PrimeTime, Tempus, ICC2, Innovus, Hspice, FineSim, PT/Tempus, TCL, Perl, Python, Awk
Responsibilities
Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs; Execute timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus; Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation; Evaluate multiple timing methodologies/tools on different designs and technology nodes; Work on automation scripts within STA/PD tools for methodology development
Seniority
Senior, hands-on IC
