Staff NPU STA/Timing Engineer
Core
Plan, design, optimize, verify, and test electronic systems, specifically focusing on Static Timing Analysis (STA) and timing convergence for multi-mode, multi-voltage domain designs.
Role type
Staff Static Timing Analysis (STA) Engineer
Builds
Digital/Analog/RF/optical systems, equipment, and packaging for cutting-edge products
Domain
Semiconductor hardware engineering, VLSI, ASIC back-end design
Required skills
Static Timing Analysis (STA), timing analysis and validation, timing constraints management, automation scripting (TCL/Perl/Python), digital flow design implementation, circuit simulations, signal integrity analysis
Preferred skills
AOCV/POCV concepts, Clock Tree Synthesis (CTS), multi-cycle path handling, layout parasitic extraction, Spice simulation correlation, device physics knowledge
Technologies
Prime-time, Tempus, ICC2, Innovus, Hspice, FineSim, PT/Tempus
Responsibilities
STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs; Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus; Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation; Evaluate multiple timing methodologies/tools on different designs and technology nodes; Work on automation scripts within STA/PD tools for methodology development
Seniority
Staff, hands-on IC
