IC Package Design Engineer, Staff
Core
Lead advanced package selection, physical design, layout, and optimization for high-performance, energy-efficient server SoCs and SiPs in data center applications.
Role type
Staff IC Package Design Engineer
Builds
High-performance server solutions and advanced package structures for data center chips
Domain
Semiconductor packaging and data center hardware
Required skills
Cadence APD & SiP, Siemens Xpedition Package Designer (xPD), Constraint Manager, DFM/ERC verification, signal-integrity for high-speed IO, chip-package-board interaction, electronic packaging processes
Preferred skills
Master's degree in EE/ME/Materials Science, 5+ years experience, Flip chip BGA/2.5D/3D Interposer, Cadence Allegro, SI/PI tools (XtractIM, PowerSI, HFSS, Q3D), substrate manufacturing, DDR/PCIe/UCIE interfaces, Calibre, high-speed layout constraints
Technologies
Cadence APD, Siemens Xpedition, Cadence Allegro, XtractIM, PowerSI, HFSS, Q3D, Calibre
Responsibilities
Own and drive advanced package selection and new generation product package structure; Responsible for Package/SiP physical design, layout, optimization, DV, and tape out; Work with multi-functional teams to achieve optimized mechanical, electrical, and thermal performance; Define and develop design verification and automation strategy; Partner with BU PD team to optimize chip Floorplan and bump placement
Seniority
Staff, hands-on IC
