Physical Design (Multiple levels)
Core
Physical Design Engineer executing the full physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs.
Role type
Senior IC Physical Design Engineer
Builds
High-performance computing, AI, mobile, automotive, and data center SoCs and ASICs
Domain
Semiconductor / VLSI Design
Required skills
Floorplanning, Clock Tree Synthesis (CTS), Placement, Routing, Timing Closure, Power Planning, IR-drop Analysis, RC Extraction, Physical Verification, Formal Verification, ECOs, Scripting (Python, Perl, TCL, Shell), C/C++, Linux/Unix
Preferred skills
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, DFT-aware implementation, Low-power design methodologies, Signal integrity analysis, MMMC sign-off flows
Technologies
Cadence Innovus, Synopsys Fusion Compiler, Synopsys PrimeTime SI, Python, Perl, TCL, Shell, C/C++, Linux, Unix
Responsibilities
Execute and drive all stages of the physical design flow from synthesized netlist to tape-out; Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs; Perform floorplanning, partitioning, power planning, and IR-drop analysis; Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios; Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations; Perform RC extraction, physical verification, and formal verification activities; Implement engineering change orders (ECOs) and support design convergence through sign-off.
Seniority
Mid-Senior, hands-on IC
