Physical Design Engineer, Staff - Hod Hasharon
Core
Lead block-level and subsystem-level physical implementation for high-performance, low-power ASICs, driving timing closure and physical sign-off on advanced process nodes.
Role type
Staff Physical Design Engineer (Backend)
Builds
Digital blocks and subsystems for high-performance, low-power world-class products
Domain
Semiconductor / ASIC Physical Design
Required skills
Floorplanning, Placement, CTS, Routing, Optimization, Timing Closure, Clock Skew Balancing, OCV Handling, MCMM Analysis, ECO Implementation, Signal Integrity Analysis, Power Integrity Analysis, IR Drop Analysis, Electromigration Analysis, DRC, LVS, DFM, EM/IR Verification, Python Scripting, TCL Scripting, Flow Development, Multi-Vt Optimization, Clock Gating, Power-Aware Synthesis
Preferred skills
Agentic AI methodologies, DFT concepts (scan insertion, ATPG, BIST)
Technologies
Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime, RedHawk, Voltus, TSMC N5/N4P/N3
Responsibilities
Lead floorplanning, placement, CTS, routing, and optimization for high-speed digital blocks; Drive timing closure including clock skew balancing, OCV handling, MCMM analysis, and ECO implementation; Conduct and own signal integrity, power integrity, IR drop, and electromigration analysis; Run full signoff verification flows (DRC, LVS, DFM, EM/IR); Develop and maintain backend PD flows using Python and TCL-based automation; Drive Agentic AI integration for automated constraint optimization and violation triage; Optimize power and area via Multi-Vt optimization, clock gating, and power-aware synthesis; Collaborate cross-functionally to resolve design and manufacturing issues
Seniority
Staff, hands-on IC
