PDK Extraction Lead Engineer
Core
Lead engineer for Physical Design Kit (PDK) extraction flows, maintaining and improving physical verification methodology for chip tapeouts.
Role type
Senior IC physical verification engineer (PDK extraction)
Builds
Custom parasitic extraction flows and verification runsets for digital, custom, and analog designs
Domain
Semiconductor hardware engineering (IC design, physical verification)
Required skills
Calibre/ICV runset coding, StarRC/Calibre-xACT/QRC flow development, DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna checks, SKILL/Python/Unix/Perl/TCL scripting, Field solvers, RC reduction tools, FINFET/Planar/SOI process knowledge
Preferred skills
Deep sub-micron technology expertise, transistor-level extraction solutions
Technologies
Calibre, ICV, StarRC, Calibre-xACT, QRC, SKILL, Python, Unix, Perl, TCL
Responsibilities
Maintain and improve physical verification flow and methodology, code custom checks (Layout/Programmable ERCs, custom LVS devices, custom DRCs), integrate and setup Calibre LVS with StarRC/QRC, revamp/rewrite PEX flows, support design teams with PEX and PV challenges, collaborate with tool vendors and foundries
Seniority
Senior, hands-on IC
