ASIC DTCO, Timing and Technology Engineer
Core
DTCO and Timing Engineer evaluating process technology entitlement (PPAY) for SOC products at block/IP and system levels in advanced process technologies (5nm, 4nm, 2nm).
Role type
Senior IC ASIC DTCO and Timing Engineer
Builds
SOC products for Mobile, Compute, Automotive, and IoT markets
Domain
Semiconductor / ASIC Design / Advanced Process Technologies
Required skills
Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre), Static Timing Analysis (STA) using PT/PT-SI and Tempus, Block level PPA analysis/implementation (RTL to GDS flow), Hard macros design implementation, Fmax optimization, PPAY optimization, Cost reduction, Python, Perl, TCL, Unix shell, C/C++
Preferred skills
ML modeling
Technologies
Hspice, Finesim, PrimeSim, AFS, Spectre, PT, PT-SI, Tempus, FC Synthesis, FC Place and Route, Genus, Innovus
Responsibilities
Evaluate process technology entitlement (PPAY) for SOC products at block/IP-level and system-level; Perform Spice simulations for power and performance validation and STA sign off; Responsible for block level PPA analysis/implementation for hard macros; Drive Fmax optimization, PPAY and cost improvements/reduction with foundry DTCO team, EDA companies, CAD team and IP team; Improve design convergence process across the company and support new advanced process technologies bring-up from PDK to VLSI design.
Seniority
Mid-Senior, hands-on IC
