Standard Cell Layout Engineer
Core
Design and develop physical layouts for logic standard cells using industry-standard CAD tools to deliver efficient and scalable physical layout designs for advanced semiconductor technology nodes.
Role type
Standard Cell Layout Engineer
Builds
High-quality intellectual property (IP) for advanced semiconductor technology nodes
Domain
Semiconductor / IC Design
Required skills
CMOS technology, integrated circuit (IC) design principles, Design Rule Checks (DRC), Layout Versus Schematic (LVS), Electrical Rule Checks (ERC), Cadence Virtuoso, SKILL scripting, Python, Design Management software
Preferred skills
Parasitic effects, reliability considerations in advanced IC designs, FinFET and Gate-All-Around (GAA) nodes
Technologies
Cadence Virtuoso, SKILL, Python
Responsibilities
Design and develop physical layouts for logic standard cells; Perform comprehensive layout verification including DRC, LVS, and ERC; Collaborate with circuit designers to ensure layouts meet quality, performance, and reliability requirements; Maintain and manage layout databases; Identify and resolve design- and PDK-related issues; Work closely with Circuit Designers and Mask Layout Designers across global development sites.
