HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required)
Core
Senior/Staff Physical Design Engineer responsible for RTL-to-GDSII flow, floorplanning, clock tree synthesis, place-and-route, timing closure, and physical verification for complex ASIC designs.
Role type
Senior/Staff IC physical design engineer (ASIC)
Builds
High-performance, low-power ASIC chips (SoC)
Domain
Semiconductor / ASIC Physical Design
Required skills
Floorplanning, Clock Tree Synthesis (CTS), Place-and-Route (PnR), Static Timing Analysis (STA), DRC/LVS verification, TCL/Python/Perl scripting, Power optimization (UPF/CPF), ECO implementation
Preferred skills
Custom clock tree architectures (H-tree, mesh), EM/IR analysis, Thermal-aware clocking, High-speed interface clocking (SerDes, DDR, PCIe), Package-level clock planning
Technologies
Innovus, ICC2, PrimeTime, Calibre, Pegasus, ICV, Synopsys, Cadence Tempus, 7nm/5nm/3nm FinFET
Responsibilities
Execute floorplanning, placement, CTS, and routing using industry-standard tools; Drive timing closure across multiple corners and modes; Optimize design for power, performance, and area (PPA); Conduct formal equivalence checks between RTL and netlist; Support physical verification including DRC, LVS, and antenna checks; Collaborate with foundries to ensure compliance with design rule manuals (DRMs); Develop and maintain automation scripts for verification flows; Debug and resolve physical verification violations; Perform full-chip static timing analysis (STA) and develop timing constraints (SDC); Define and implement low-power architecture using CLP methodology; Interface with EDA vendors to resolve tool issues.
Seniority
Senior/Staff, hands-on IC
