Staff Engineer, ASIC STA
Core
Staff Engineer leading Static Timing Analysis (STA), Synthesis, and Logic Equivalence Checking (LEC) for complex mixed-signal ASIC designs to ensure silicon success.
Role type
Staff Engineer, ASIC STA
Builds
High-frequency, multi-GHz ASIC builds with low-power domains and complex IPs
Domain
Semiconductor / ASIC Design
Required skills
Static Timing Analysis (STA), Synthesis, Logic Equivalence Checking (LEC), Mixed-signal IP integration, Timing closure, Hierarchical design, High-frequency clock management, Scripting and automation, EDA tools, Low-power design, AI-enabled workflows
Technologies
EDA tools, Scripting languages
Responsibilities
Manage synthesis to timing closure, Develop constraints and timing models, Identify and meet requirements for critical paths of multi-GHz builds, Integrate new mixed signal complex IPs, Collaborate in multi-functional and globally dispersed teams
Seniority
Staff, hands-on IC
