Principal Engineer- HIG HBM Layout
Core
Designing and developing complex Application-Specific Integrated Circuits (ASICs) for High Bandwidth Memory (HBM) products serving AI and high-performance computing applications.
Role type
Principal Engineer (Analog/Mixed-Signal Layout & Team Leadership)
Builds
High Bandwidth Memory (HBM) chips and custom analog/mixed-signal layouts
Domain
Semiconductor / VLSI / Memory Technology
Deliverable
production ML models | product features | infrastructure
Required skills
Analog/custom layout design, floor planning, manual routing, high-speed interface principles, mixed-signal design, off-chip signaling, Cadence VLE/VXL, Calibre DRC/LVS, team building, project management
Preferred skills
Industry standards committee participation, multi-site collaboration
Technologies
Cadence VLE, Cadence VXL, Calibre
Responsibilities
Lead the establishment and growth of a layout team to meet global HBM requirements; design and develop complex ASICs for HBM; ensure architecture analysis and optimization for performance, power, and area; generate and communicate design specifications; manage multiple custom IC layout projects from start to tape-out; assist customers in product implementation.
Seniority
Principal, hands-on IC design with strategic team leadership