MTS Process Integration Engineer | APTD Die Level Technology
Core
Develop and integrate advanced package architectures (2.5D, 3D stacking, HBM, hybrid bonding) to enable AI and high-performance computing applications.
Role type
Senior IC process integration engineer (advanced packaging)
Builds
Next-generation memory and storage packaging solutions for AI and HPC
Domain
Semiconductor manufacturing / Advanced Packaging
Required skills
Advanced packaging technology development, 2.5D/3D integration, HBM integration, hybrid bonding, TSVs, advanced interconnects, die stacking, underfill, molding, bonding, package integration, warpage engineering, thermal optimization, cross-functional program management
Preferred skills
Thermocompression bonding, microbump development, interposer-based packaging, data analytics, automation, AI-enabled workflows, technical publication authoring
Technologies
SPC, inline metrology, modeling tools, cure-shrinkage control systems
Responsibilities
Develop and optimize advanced packaging technologies; Design and execute experiments to qualify materials and process flows; Analyze yield, performance, and defect data; Drive technology transfer and manufacturing readiness; Predict and mitigate wafer/die warpage; Collaborate with design, process, equipment, reliability, test, and manufacturing teams
Seniority
Senior, hands-on IC (via careerplan.io/jobs/44489731-mts-process-integration-engineer-aptd-die-level-technology-at-micron)
