Physical Design Intern
Core
Intern role supporting block-level physical implementation for ultra-low power System-on-Chip (SoC) designs in advanced process nodes.
Role type
Physical Design Intern (SoC)
Builds
Ultra-low power semiconductor chips for wearables, medical devices, IoT, and AI edge applications
Domain
Semiconductor / VLSI / Low-power SoC design
Deliverable
production ML models | product features
Required skills
Digital logic design, VLSI/physical design/ASIC design, CMOS circuits, Verilog/VHDL, placement, routing, timing closure, clock trees, power grid planning, Linux/UNIX environment
Preferred skills
Computer architecture
Technologies
Tcl, Python, Shell, physical implementation tools, static timing analysis (STA) tools
Responsibilities
Assist with floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure; Run and analyze static timing analysis (STA) and debug timing violations; Help perform power, signal integrity, and IR drop analysis; Contribute to design rule check (DRC) and layout versus schematic (LVS) closure; Develop and maintain automation scripts; Document methods and present progress to mentor
Seniority
Intern