PRINCIPAL ENGINEER, DDEG DESIGN METHOD
Core
Lead verification and end-to-end analysis for sophisticated full-chip gate-level custom designs in advanced low-power and power management technologies (DDR4, LPDDR4, DDR5, LPDDR5) operating at high speeds up to 6400MT/s.
Role type
Principal Engineer, DDEG Design Method (Verification)
Builds
High-speed DRAM and emerging memory architectures
Domain
Semiconductor / Memory / Digital & Mixed-Signal Verification
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, SPICE, gate-level circuit analysis, AI tool validation, test-bench development, regression analysis, mixed-signal verification
Preferred skills
Real Number Models, Perl/Python scripting, DRAM memory domain experience, Virtuoso/Xcellium/Simvision tooling
Technologies
Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice, SystemVerilog, UVM, Perl, Python
Responsibilities
Accelerate verification cycle time using AI-based tools and automation frameworks; validate AI outputs against specs and simulations; develop test cases and stimulus for functional coverage; maintain test benches and run regressions; participate in developing verification methodology and environments.
Seniority
Principal, hands-on IC with mentorship
