Digital Physical Implementation and Integration Engineer
Core
Design and analyze digital/analog circuits for memory products, owning physical implementation and top-level integration of large digital designs in NAND products.
Role type
Senior IC physical design engineer (memory)
Builds
NAND memory chips and silicon-to-systems solutions
Domain
Semiconductor / Memory / Physical Design
Required skills
Static timing analysis (STA), Digital physical design (floorplan, place, route, CTS), Synthesis, Physical verification (DRC, LVS, EM/IR), Tcl/Python automation, CMOS logic, Standard cells, Low-power techniques
Preferred skills
Multi-partition SoC integration, Clock planning, DFT/scan compression, EDA-vendor AI tools
Technologies
Cadence Innovus, Synopsys ICC2/Genus, Calibre, PrimeTime, Design Compiler, Linux/Unix, Git
Responsibilities
Lead layout process (floor-planning, placement, routing), Perform top-level virtual flat placement and global routing, Drive block-level APR flow (init to sign-off), Automate flows using Tcl/Python/SKILL, Collaborate with cross-functional teams for manufacturability
Seniority
Senior, hands-on IC
