HBM SoC Physical Design Engineer
Core
Drive physical implementation of advanced HBM SoC logic/base die designs from netlist to GDSII, ensuring robust signoff and tape-out readiness.
Role type
Senior IC physical design engineer (SoC/HBM)
Builds
HBM SoC logic and base die designs for memory and storage solutions
Domain
Semiconductor / SoC Physical Design
Required skills
SoC physical design implementation, EDA tools (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre), STA fundamentals, clocking, constraints (SDC), power intent (UPF/CPF), physical verification (DRC/LVS/ERC)
Preferred skills
HBM/DRAM adjacent SoC design experience, mentoring early-career engineers, Agentic AI workflow development
Technologies
Cadence Innovus, Tempus, Synopsys ICC2, PrimeTime, Siemens Calibre, UPF, CPF, SDC
Responsibilities
Own physical implementation (floor-planning, placement, CTS, routing, optimization), drive timing closure across MMMC scenarios, integrate complex IP, perform physical signoff (DRC/LVS/IR drop/EM), partner with DFT teams, support tape-out execution, improve productivity via scripting/automation
Seniority
Senior, hands-on IC
