Senior PD Engineer: Synthesis & STA
Core
End-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips, acting as a bridge between front-end design and back-end physical implementation teams.
Role type
Senior IC VLSI Synthesis & STA Engineer
Builds
ASIC/SoC logic blocks and sub-chips optimized for area, power, and performance
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (specifically: synthesis flows, netlists, timing signoff)
Required skills
Logic Synthesis, Static Timing Analysis (STA), Verilog/SystemVerilog, Tcl/Python/Perl scripting, RTL linting, CDC analysis, Multi-mode Multi-corner (MMMC) analysis, Netlist optimization, Timing constraints (SDC)
Preferred skills
Place and Route (PNR) flows, Formal Verification (LEC/Formality), Advanced technology nodes (5nm/3nm)
Technologies
Cadence Genus, Tempus, PrimeTime, Innovus, ICC2
Responsibilities
Drive complete logic synthesis process for designated blocks; Define and execute quality signoff checks; Collaborate with RTL engineers to ensure clean netlist handoff; Optimize Levels of Logic (LOL) and timing paths; Provide micro-architecture guidance and RTL coding guidelines; Participate in PNR execution and full-chip timing convergence
Seniority
Senior, hands-on IC
