Sr. Manager, Physical Design Engineering, Annapurna Labs
Core
Lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs (Inferentia, Trainium) on advanced tech nodes.
Role type
Senior Manager, Physical Design Engineering
Builds
Custom SoCs for AWS cloud infrastructure ML servers
Domain
Semiconductor / ASIC Physical Design / AI/ML Accelerators
Deliverable
production ML models
Required skills
People management (8+ engineers), ASIC/SoC physical design (7nm-3nm), RTL-to-GDSII flow, EDA tool mastery (Synopsys, Cadence, Siemens), Advanced STA, Power integrity, High-speed PD, Hierarchical methodologies, Scripting (TCL, Python, Perl)
Preferred skills
AI/ML accelerator leadership, 3nm GAA/Nanosheet, 2.5D/3D integration, AI/ML-driven design automation, Multi-foundry assessment
Technologies
Synopsys Fusion Compiler/ICC2/PrimeTime/StarRC/RedHawk-SC, Cadence Innovus/Tempus/Quantus/Voltus, Siemens Calibre, TSMC, Samsung, Intel Foundry Services
Responsibilities
Build and scale PD team, Own physical design strategy and roadmap, Institutionalize PPA improvement, Provide hands-on technical leadership on timing closure and high-speed I/O, Lead technology node enablement, Define RTL2GDS methodologies, Serve as technical interface with foundry/EDA vendors, Own tapeout execution
Seniority
Senior Manager, hands-on technical leadership