STAFF ENG-HBM-LAYOUT
Core
Staff Layout Design Engineer responsible for mixed-signal, custom digital block, and full chip level integration for High Bandwidth Memory (HBM) solutions targeting AI and high-performance computing.
Role type
Staff IC Layout Design Engineer
Builds
PWF Reticles, advanced packaging designs, and full chip layouts for HBM
Domain
Semiconductor / Memory / Advanced Packaging
Required skills
Mixed-signal layout design, Custom digital block design, Full chip integration, PWF Reticle design, TSV design, DFMEA creation, LVS/DRC/Antenna verification, Layout automation/AI usage, Physical verification, Project management, Team leadership
Preferred skills
Multiple tape-out support experience, Managing multiple layout projects
Technologies
Cadence VLE/VXL, Mentor Graphic Calibre
Responsibilities
Design and co-optimization of critical mixed-signal and custom digital blocks, Build and tapeout PWF Reticles, Engage with Scribe Design team for advanced packaging requirements, TSV design engagement for electrical/thermal/mechanical performance, Creation and maintenance of DFMEA for advanced packaging, Perform layout verification (LVS/DRC/Antenna), Guide junior team members in sub block-level layouts, Contribute to effective project management
Seniority
Staff, hands-on IC with leadership
