Substrate IC Package Layout Design Engineer

Taipei💼 Full-time🗓 2026-09-17 → 2026-09-25

Core

End-to-end design of complex IC substrate packages for high-power AI processors and accelerators, focusing on power delivery and high-speed signaling.

Role type

Senior IC Package Layout Design Engineer

Builds

High-performance AI inference chips (ASICs) for transformers

Domain

Semiconductor hardware / AI infrastructure

Deliverable

production ML models

Required skills

IC substrate layout design, high-power package design (>700W), high-speed signal routing (>50GHz), CoWoS interposer design, DRC/LVS verification, Allegro Package Designer, SI/PI principles

Preferred skills

Experience with large substrate designs (>50mm), cross-functional co-design with silicon/system teams

Technologies

Allegro Package Designer

Responsibilities

Lead design and development of complex IC substrate layouts; Develop high-speed signal routing solutions; Optimize CoWoS interposer designs; Perform DRC and LVS verification; Collaborate with SI/PI engineers on integrity requirements

Seniority

Senior, hands-on IC

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About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on **inference**. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.