SoC Physical Verification Engineer, HBM
Core
Define, execute, and drive sign-off quality physical verification flows for next-generation HBM logic die and memory-centric SoCs, ensuring design integrity from layout through first silicon.
Role type
Senior IC SoC Physical Verification Engineer (HBM)
Builds
Tape-out-ready silicon for Heterogeneous Integration Group (HIG) products
Domain
Semiconductor / Advanced Node SoC / HBM
Deliverable
production ML models
Required skills
Full-chip physical verification (DRC, LVS, ERC, PERC, DFM), Foundry rule deck management, Reliability verification (ESD, latch-up, electromigration), Python/Tcl/Perl scripting, AI/ML tool adoption
Preferred skills
HBM/DRAM/2.5D/3D integration experience, GPU/CPU/accelerator implementation background, Post-silicon failure analysis correlation
Technologies
Calibre, IC Validator (ICV), Pegasus, Python, Tcl, Perl
Responsibilities
Implement physical verification sign-off for full-chip and hierarchical designs; Implement and debug foundry-qualified rule decks; Perform reliability verification across multiple power domains; Run density, metal fill, and CMP checks; Perform parasitic RC extraction and support correlation with post-silicon measurements; Develop and optimize physical verification flows and automation; Drive adoption of AI/ML-based verification tools; Partner with physical design, EDA, and foundry teams
Seniority
Senior, hands-on IC
