Engineer-std cell layout
Core
Design and maintain standard cell layouts for new DRAM products on emerging technologies, leading projects from specification to PPA-qualified library release.
Role type
Senior IC physical design engineer (standard cells)
Builds
Standard cell libraries for DRAM products
Domain
Semiconductor manufacturing / Memory (DRAM) / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Standard cell layout, LVS/DRC/Latchup verification, project planning and scheduling, team leadership, process-CAD negotiation, AI tool integration, flow development
Preferred skills
Emerging technology architecture development, AI-assisted workflow automation
Technologies
DTCO tools, CMOS processes, CAD tools, AI tools
Responsibilities
Design and maintain standard cells layout for new DRAM products on new technology; Lead stdcells layout projects from initial spec definition to PPA qualified library release; Collaborate with DTCO team to develop stdcells architecture for emerging technologies; Perform layout verification like LVS/DRC/Latchup, quality check and documentation; Responsible for on-time delivery of block-level layouts with acceptable quality; Guide junior team-members in their execution of Sub block-level layouts & review their work; Develop new flows/methodologies to reduce the stdcells manual effort & increase the productivity; Work with Process team, CMOS and CAD to negotiate drc for new technology; Leverage AI tools to automate the tools and workflow; Use AI-assisted workflows to improve design productivity
Seniority
Senior, hands-on IC with leadership responsibilities