New College Grad - HBM Layout Engineer
Core
Design layout for leaf cells, standard cells, or sub-blocks in ICs, ensuring design accuracy through physical verification checks.
Role type
junior IC layout engineer
Builds
pre-silicon circuit designs and layout structures
Domain
semiconductor manufacturing / physical design
Required skills
IC layout design, DRC/LVS interpretation, circuit simulation, electronic circuit concepts, project planning
Preferred skills
pre-silicon circuit design, analog circuits, MOS concepts, semiconductor fabrication, layout trade-offs, scripting (C++, Python), Cadence VLE/VXL, Mentor Graphics Calibre
Technologies
Cadence VLE/VXL, Mentor Graphics Calibre, circuit simulation tools
Responsibilities
Design layout for leaf cells, standard cells, or sub-blocks; Apply systematic approach to IC layout design; Interpret DRC/LVS and physical verification checks; Plan work to meet project timelines; Collaborate with internal teams for project execution
