Photonics Layout Engineer
Core
Creating, optimizing, and validating photonic integrated circuit (PIC) layouts to ensure manufacturability and performance for silicon photonics systems.
Role type
Photonics Layout Engineer (via careerplan.io/jobs/05-00B-7E-C6C-photonics-layout-engineer-at-dustphotonics)
Builds
Photonic integrated circuits (PICs) for data centers, healthcare, LIDARs, and sensors
Domain
Silicon Photonics / Semiconductor Manufacturing
Required skills
Cadence Virtuoso, DRC/LVS verification, foundry PDKs, PCell development, SKILL scripting, waveguide routing, layout optimization
Preferred skills
Silicon photonics fabrication process knowledge, mixed photonic-electronic layout integration
Technologies
Cadence Virtuoso, SKILL
Responsibilities
Develop and implement mask layouts for PICs using Cadence Virtuoso; Create and maintain PCells for photonic building blocks; Perform waveguide routing ensuring correct connectivity and low-loss optical paths; Verify layouts using DRC and LVS to ensure compliance with foundry requirements; Collaborate with device designers to translate schematics into manufacturable layouts; Optimize layouts for performance, yield, and compactness; Participate in photonic design automation tool development; Prepare and manage data for tape-out and support mask review processes; Debug layout and rule-check issues and propose corrective actions.